1 ? fn6189.4 isl45041 tft-lcd i 2 c programmable vcom calibrator the v com voltage of an lcd panel needs to be adjusted to remove flicker. this part provid es a digital interface to control the sink-current output that at taches to an external voltage divider. the increase in output sink current lowers the voltage on the external divider, which is applied to an external v com buffer amplifier. the desired v com setting is loaded from an external source via a standard 2-wire i 2 c serial interface. at power up, the part automatically comes up at the last programmed eeprom setting. an external resistor attaches to the set pin and sets the full-scale sink current that det ermines the lowest voltage of the external voltage divider. the isl45041 is available in an 8 ld 3mm x 3mm tdfn package with a maximum thickness of 0.8mm for ultra thin lcd panel design. an evaluation kit complete with software to control the dcp from a computer is available. reference application note an1275 and ?ordering information?. features ? 128-step adjustable sink current output ? 2.25v to 3.6v logic supply voltage operating range (2.6v minimum programming voltage) ? 4.5v to 18v analog supply voltage operating range (10.8v minimum programming voltage) ?i 2 c interface with addresses 100111x and 100110x ? on-chip 7-bit eeprom ? output adjustment set pin ? output guaranteed monotonic over-temperature ? thin 8 ld 3mm x 3mm dfn (0.8mm max) ? pb-free (rohs compliant) applications ? lcd panels pinout isl45041 (8 ld tdfn) top view ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl45041irz 041z 0 to +85 8 ld 3x3 tdfn l8.3x3a isl45041eval1z evaluation board note: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity le vel (msl), please see device information page for isl45041 . for more information on msl, please see technical brief tb363 . out avdd wp gnd 1 2 3 4 8 7 6 5 set scl sda vdd pad data sheet december 17, 2010 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2005- 2007, 2010. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
2 fn6189.4 december 17, 2010 pin descriptions pin type pull u/d function out output adjustable sink current output pin. the current that sinks into the out pin is equal to the dac setting times the maximum adjustable sink current di vided by 128. see set pin function description for the maximum adjustable sink current setting. av dd supply high-voltage analog supply. bypa ss to gnd with 0.1f capacitor. wp input pull-down write protect. active low. to enable programming, connect to 0.7*v dd supply or greater. the wp pin is designed for static control. it has an internal pull-down current sink. to avoid the possibly over-writing the eeprom contents, no frequency above 1hz should be applied to this input. care should be taken to avoid any glitches on the input. when re moving or applying mechanical jumpers, always ensure the v dd power is off. a high to low transition on the wp pin results in the register contents being loaded with eeprom data. gnd supply ground connection. v dd supply digital power supply input. by pass to gnd with 0.1f capacitor. sda in/out i 2 c serial data input and output. scl input i 2 c clock input set analog maximum sink current adjustment point. connect a re sistor from set to gnd to set the maximum adjustable sink current of the out pin. the maximum adjustable sink current is equal to (av dd /20) divided by rset. block diagram gnd i 2 c interface dac registers analog dcp and current sink 7-bit eeprom scl sda wp v dd a vdd out set 1 8 2 5 7 6 3 4 isl45041 current sink q1 a1 isl45041
3 fn6189.4 december 17, 2010 absolute maximum rati ngs thermal information v dd to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4v input voltages to gnd set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +4v avdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +20v output voltages to gnd out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +a vdd esd rating human body model device (tested per jesd22-a114e). . . . . . . . . . . . . . . . . . 2kv input pins (scl, sda) (tested per jesd22-a114e) . . . . . . . 4kv operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +85c thermal resistance (typical) ja (c/w) jc (c/w) 8 ld tdfn package (notes 4, 5). . . . . 53 11 moisture sensitivity (see technical brief tb363) all packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . level 2 maximum junction temperature (plastic package) . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications test conditions: v dd = 3.3v, av dd = 18v, r set = 5k ? , r1 = 10k ? , r2 = 10k ? ; (see figure 1) unless otherwise specified. typicals are at t a = +25c. boldface limits apply over the operating temperature range, 0c to +85c. parameter symbol test conditions min (note 6) typ max (note 6) units power supply characteristics v dd supply range supporting eeprom programming v dd 2.6 3.6 v av dd supply range supporting eeprom programming av dd 10.8 18 v v dd supply range for wide-supply operation (not supporting eeprom programming) v dd 2.25 3.6 v av dd supply range for wide-supply operation (not supporting eeprom programming) av dd 2.6v < v dd < 3.6v 4.5 18 v 2.25v < v dd < 2.6v 4.5 13 v v dd supply current i dd (note 7) 65 a av dd supply current i avdd (note 8) 38 a dc characteristics set voltage resolution set vr 7 7 7 bits set differential nonlinearity set dn monotonic over-temperature 1 lsb set zero-scale error set zse 3 lsb set full-scale error set fse 8 lsb set current (r set = 24.9k and av dd = 10v) iset through r set (note 11) 20 a set external resistance set er to gnd, av dd = 18v 5 200 k to gnd, av dd = 4.5v 2.25 45 k to gnd, av dd = 15v, v dd = 3v v out > 2.5v (note 12) 1.0 200 k av dd to set voltage attenuation avdd to set (note 9) 1:20 v/v out settling time out st to 0.5 lsb error band (note 9) 8s out voltage range v out v set +0.5v 13 v set voltage drift set vd 25c < t a < 55c (note 9) <10 mv isl45041
4 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6189.4 december 17, 2010 sda, scl input logic high i 2 cv ih 0.7*v dd v sda, scl input logic low i 2 cv il 0.55 v sda, scl hysteresis (note 9) 260 mv sda output logic high voh s v dd - 0.4 v sda output logic low vol s @ 3ma 0.4 v wp input logic high v ih 0.7*v dd v wp input logic low v il 0.3*v dd v wp hysteresis (note 9) 0.14v dd v wp input current il wpn 0.20 35 a i 2 c timing scl clock frequency f scl 0 400 khz i 2 c clock high time t sch 0.6 s i 2 c clock low time t scl 1.3 s i 2 c spike rejection filter pulse width t dsp 050 ns i 2 c data set up time t sds 100 ns i 2 c data hold time t sdh 900 ns i 2 c sda, scl input rise time t icr dependent on load (note 10) 20 + 0.1*cb 1000 ns i 2 c sda, scl input fall time t icf (note 10) 20 + 0.1*cb 300 ns i 2 c bus free time between stop and start t buf 200 s i 2 c repeated start condition set-up t sts 0.6 s i 2 c repeated start condition hold t sth 0.6 s i 2 c stop condition set-up t sps 0.6 s i 2 c bus capacitive load cb 400 pf sda pin capacitance c sda 10 pf scl pin capacitance c s 10 pf eeprom write cycle time t w 100 ms notes: 6. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. i dd current may increase to 2ma for 45ms or less during each eeprom programming operation. 8. i avdd current may increase to 1ma for 30ms or le ss during each eeprom programming operation. 9. simulated and determined via design and not directly tested. 10. simulated and designed according to i 2 c specifications. 11. a typical current of 20 a is calculated using av dd = 10v and r set = 24.9k . reference ?r set resistor? in figure 2. 12. minimum value of r set resistor guaranteed when: av dd = 15v, v dd = 3.0v and when voltage on the vout pin is greater than 2.5v. reference equation 2 on page 5 with setting = 128. electrical specifications test conditions: v dd = 3.3v, av dd = 18v, r set = 5k ? , r1 = 10k ? , r2 = 10k ? ; (see figure 1) unless otherwise specified. typicals are at t a = +25c. boldface limits apply over the operating temperature range, 0c to +85c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units isl45041
5 fn6189.4 december 17, 2010 application information this device provides the ability to reduce the flicker of an lcd panel by adjustment of the v com voltage during production test and alignment. a 128-step resolution is provided under digital control, which adjusts the sink current of the output. the output is connected to an external voltage divider, so that the device will have the capability to reduce the voltage on the output by increasing th e output sink current. the adjustment of the output is provided by the 2-wire i 2 c serial interface. expected output voltage the isl45041 provides an output sink current, which lowers the voltage on the external voltage divider (v com output voltage). equation 1 and equation 2 can be used to calculate the output current (i out) and output voltage (v out ) values. the setting is the register value +1 with a value between 1 and 128. table 1 gives the calculated value of v out using the resistor values of: r set = 24.9k , r 1 = 200k , r 2 = 243k , and av dd =10v. r set resistor the external r set resistor sets the full-scale sink current, i set maximum, that determines the lowest voltage of the external voltage divider r 1 and r 2 (figure 1). the voltage difference between the out pin and set pin (figure 2), which are also the drain and source of the output transistor, must be greater than 1.75v. this will keep the output transistor in its saturation region to maintain linear operation over the full range of register values. expected current settings and 7-bit accuracy occurs when the output mos transistor is operating in the saturation region. figure 2 shows the internal connection for the output mos transistor. the value of the av dd supply sets the voltage at the source of the output transistor. this voltage is equal to (setting/128) x (av dd /20). the i set current is therefore equal to (setting/128) x (av dd /20 x r set ). the drain voltage is calculated using equation 2. the values of r 1 and r 2 (equation 2) should be determined using i out maximum (setting equal to 128) so the minimum value of v out is greater than 1.75v + av dd /20. ramp-up of the vdd power supply the ramp-up from 10% v dd to 90% v dd level must be achieved in 10ms or less to ensure that the eeprom and power-on-reset circuits are synchronized and the correct value is read from the eeprom memory. power supply sequence the recommended power supply sequencing is shown in figure 3. when applying power, vdd should be applied before or at the same time as avdd. the minimum time for t vs is 0s. when removing power, the sequence of vdd and avdd is not important. do not remove vdd or avdd within 100ms of the start of the eeprom programming cycle. re moving power before the eeprom programming cycle is completed may result in corrupted data in the eeprom. table 1. setting value v out 1 5.486 10 5.313 20 5.141 30 4.969 40 4.797 50 4.625 60 4.453 70 4.281 80 4.109 90 3.936 100 3.764 110 3.592 128 3.282 r set figure 1. output connection circuit example - + isl45041 set out avdd r 1 r 2 avdd i out i out setting 128 -------------------- - x av dd 20 r set () --------------------------- = v out r 2 r 1 r 2 + -------------------- - ?? ?? ?? av dd 1 setting 128 -------------------- - x r 1 20 r set () --------------------------- ? ?? ?? ?? = (eq. 1) (eq. 2) figure 2. output connection circuit example av dd = 15v r set out pin r1 r2 avdd vsat set pin setting 128 ---------------------------- x av dd 20 ----------------- - 0.5v figure 3. power supply sequence v dd a vdd t vs isl45041
6 fn6189.4 december 17, 2010 i 2 c bus format. i 2 c addressing the isl45041 will respond identically to either of two i 2 c address: 100111 0 x and 100111 1 x. 100111x is the preferred address. to prevent bus conflict s, ensure that there are no other devices on the i 2 c bus with either of the above addresses. figure 4. isl45041 i 2 c read and write format 6 bit address start r/w ack data ack stop 10 01 1 1 1 x d7 d6 d5 d4 d3 d2 d1 a a isl45041 i 2 c read format r/w = 0 = write r/w = 1 = read d0 start byte 1 byte 2 msb lsb msb lsb 6 bit address start r/w ack data program ack don?t care stop 10 01 1 1 0 xd7d6d5d4d3 d2 d1 p a a isl45041 i 2 c write format r/w = 0 = write r/w = 1 = read when r/w = 0 p = 0 = eeprom programming p = 1 = register write byte 1 byte 2 msb lsb msb lsb don?t care isl45041
7 fn6189.4 december 17, 2010 isl45041 package outline drawing l8.3x3a 8 lead thin dual flat no-lead plastic package rev 4, 2/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.20mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 6x 0.65 1.50 0.10 8 1 8x 0.30 0.10 6 0.75 0.05 see detail "x" 0.08 0.10 c c c ( 2.90 ) (1.50) ( 8 x 0.30) ( 8x 0.50) ( 2.30) ( 1.95) 2.30 0.10 0.10 8x 0.30 0.05 a mc b 4 2x 1.950 (6x 0.65) index area pin 1 compliant to jedec mo-229 weec-2 except for the foot length. 7.
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